This invention relates generally to the testing of semiconductor components, and more particularly to the testing and burning-in of semiconductor components contained on a substrate, such as a semiconductor wafer.
Semiconductor components such as semiconductor dice and packages are routinely tested during manufacture. Semiconductor dice, for example, are typically fabricated on a semiconductor wafer using well known processes such as doping, masking, etching, and deposition of metals. Following fabrication of the dice, the wafer is probed and mapped to test the gross functionality of each die. A wafer prober and probe card can be used to electrically engage bond pads, or other test pads on the dice, and to apply test signals to the integrated circuits contained on the dice. The non functional dice are mapped in software or mechanically marked.
Following wafer probe, the functional dice can be singulated and packaged, or alternately retained in unpackaged form as known good die (KGD). Packaged dice are then burn-in tested by heating the dice while electrically biasing the integrated circuits on the dice. Bare dice can be burn-in tested using temporary carriers configured to temporarily package the dice. Burn-in boards are adapted to hold a large number of semiconductor packages, or temporary carriers for bare dice, in a chamber with temperature cycling capability. The burn-in boards are also in electrical communication with test circuitry configured to generate and to apply test signals to the dice.
In addition to burn-in testing, full functionality test can be performed on the packaged or bare dice to evaluate various electrical characteristics of the integrated circuits. Among the parameters that can be tested are input and output voltages, capacitance, pad leakage and current specifications. Memory devices can also be subjected to logic tests wherein data storage, retrieval capabilities, and response times are measured.
Recently, different processes have been developed for performing wafer level burn-in testing, prior to the dice being singulated from the wafer. One such process is described in U.S. Pat. Nos. 5,829,128 and 6,032,356 to Eldridge et al., which are assigned to FormFactor Inc. of Livermore, Calif. This process involves probe testing the wafer to identify functional and non-functional dice, and then attaching resilient contact structures to the bond pads on the functional dice. The resilient contact structures can then be used to establish temporary electrical connections with the dice for performing burn-in tests. In addition, the resilient contact structures can be used to provide terminal contacts for the dice following singulation from the wafer.
FIG. 1 illustrates the prior art process sequence of fabricating the dice on the wafer, probe testing to identify functional dice, attaching resilient contact structures to the functional dice, and then burn-in testing the functional dice on the wafer using the resilient contact structures.
FIG. 2A illustrates a prior art semiconductor wafer 10 which comprises a plurality of semiconductor dice 12 having resilient contact structures 14 attached to bond pads 16 (FIG. 2C) of the dice 12. The resilient contact structures 14 have been attached to the functional dice 12F on the wafer 10 responsive to wafer probe testing. As shown in FIG. 2B, each functional die 12F includes the resilient contact structures 14, while each non-functional (defective) die 12NF does not include the resilient contact structures 14. FIG. 2C illustrates the resilient contact structures 14 attached to the bond pads 16 on a functional die 12F. In addition, the resilient contact structures 14 include a core 18 which comprises a relatively low yield strength metal, and a shell 20 which comprises a relatively high yield strength metal. Both the core 18 and the shell 20 are formed with a resilient spring shape or spring segment.
FIGS. 3A-3F illustrate various prior art configurations for the resilient contact structures 14. In FIG. 3A, a resilient contact structure 14A comprises a cantilever beam oriented at an angle to a contact force F. The contact force F can be applied during formation of a pressure or bonded contact with a mating electronic component, such as a printed circuit board (PCB). In FIG. 3B, a resilient contact structure 14B includes an S-shape spring segment configured for contact by the contact force F or a contact force Fxe2x80x2. In FIG. 3C, a resilient contact structure 14C includes a U-shape spring segment configured for contact by the contact force F. In FIG. 3D, a resilient contact structure 14D includes a curved spring segment configured for contact by the contact force F. In FIG. 3E, a resilient contact structure 14E includes a C-shaped spring segment configured for contact by the contact force F. In FIG. 3F, a resilient contact structure 14F includes a spring segment configured for contact by the contact force F.
One shortcoming of the above wafer level burn-in process is that the wafer 10 must first be probe tested, and the resilient contact structures 14 attached to only the functional dice 12F. In general, the non-functional dice 12NF do not include the resilient contact structures 14 because their electrical connection to the burn-in board may compromise the burn-in test procedure. Specifically, conventional burn-in boards include a power grid for establishing temporary electrical connections to multiple dice at one time. The burn-in boards thus utilize xe2x80x9cshared resourcesxe2x80x9d to test a large number of dice at the same time. Non-functional dice 12NF can short the test signals, or otherwise adversely affect the test procedure.
In view of the foregoing, it would be desirable to have a method and system for electrically isolating resilient contact structures 14 on some of the dice 12, particularly the non functional dice 12NF. This would permit all of the dice 12 on the wafer 10 to be provided with resilient contact structures 14, such that wafer probe testing can be performed using the resilient contact structures 14. In addition, this would permit non-functional dice 12NF to be electrically isolated on a burn-in board, to permit wafer level burn-in tests to be performed.
In accordance with the present invention, a test method, and a test system, for testing and burning-in semiconductor components on a substrate are provided. In an illustrative embodiment the substrate comprises a semiconductor wafer, and the components comprise semiconductor dice fabricated on the wafer.
The test method includes the initial step of providing resilient contact structures on every component constructed as previously described. The test method also includes the step of testing the components to identify functional, and non functional (defective) components. The testing step can be performed using a wafer prober having a test board configured to electrically engage the resilient contact structures. The test method also includes the steps deforming the resilient contact structures on the non functional components to provide deformed contact structures, and then burn-in testing the functional components. The deformed contact structures on the non functional components provide electrical isolation during burn-in testing, such that burn-in can be performed using a burn-in board and test circuitry that employ xe2x80x9cshared resourcesxe2x80x9d.
Deformation of the resilient contact structures can be performed using a deformation apparatus constructed in accordance with the invention. The deformation apparatus includes a deformation block having a plurality of retention structures for physically engaging the resilient contact structures on the non functional components, and a substrate holder for holding the substrate proximate to the deformation block. Either the deformation block or the substrate holder (or both) can be configured for movement in X, Y and Z directions such that the resilient contact structures on the non functional components can be deformed by compression, bending or shaping. Movement of the deformation block, or the substrate holder (or both) can be accomplished using a wafer prober, an aligner bonder, a hexapod, or any tool that allows precision movement and placement of semiconductor components. With a wafer prober, the deformation block can be configured for positioning at the non-functional components responsive to wafer mapping software.
The test system includes the deformation apparatus for deforming the resilient contact structures on the non functional components responsive to probe testing of the substrate. The test system also includes the substrate with the resilient contact structures on each functional component, and the deformed contact structures on each non functional component. The test system also includes a burn-in board, and a burn-in oven configured to burn-in test multiple substrates at the same time. In addition, the test system includes a test board having test pads configured to electrically engage the resilient contact structures on the functional components while maintaining a space between the deformed contact structures on the non functional components. The test pads on the test board are in electrical communication with test circuitry, and are biased into electrical engagement with the resilient contact structures using a pressure plate and a spring member.
An alternate embodiment test system includes a deformation block configured to electrically engage the resilient contact structures on each component, one component at a time, and to transmit test signals to the components to identify defective components. In addition, the deformation block is configured to deform the resilient contact structures on the defective components to provide electrical isolation during a subsequent burn-in test.
An alternate embodiment planarization system includes a deformation block configured to planarize the resilient contact structures on each component. In this embodiment the deformation block can be configured to just physically engage the resilient contact structures. Alternately the deformation block can be configured to physically and electrically engage the resilient contact structures, and to transmit test signal to the components.